1. Field of the Invention
The present invention relates to a simplicity HDTV video decoder and its decoding method and, more particularly, to a simplicity HDTV video decoder and its decoding method by which a parallel decoding can be achieved respectively for luminance and color signals.
2. Discussion of Related Art
In American HDTV regulations, what are termed GA (Grand Alliance) HDTV system, the image compression and multiplex techniques are based on the MPEG-2 (Moving Picture Experts Group-2) regulations.
Various video formats are included; sequential scanning of 24 Hz and 30 Hz and interlaced scanning of 60 Hz with 1920.times.1080 pixels, and sequential scanning of 24 Hz, 30 Hz and 60 Hz with 1280.times.720 pixels. Theses video formats are based on the MPEG-2 regulations, and require large memories to realize a complete HDTV decoder.
As for a general HDTV receiver, human eyes do not sense a deterioration in the resolution even when the horizontal resolution of an image is reduced by half on a monitor which is less than 50 inches in size.
For that reason, a simplicity HDTV video decoder can be realized by reducing the horizontal video resolution and decreasing its memories.
FIG. 1 is a block diagram of a general HDTV video decoder. Referring to FIG. 1, the HDTV video decoder comprises: a VLD (Variable Length Decoder) portion 11 for variable-length-decoding an input HDTV bit stream and dividing it into a motion vector, a luminance signal and a color difference signal; a reverse quantizing portion 12 for reverse-quantizing the count number transferred from the VLD portion 11; an IDCT (Inverse Discrete Cosine Transform) portion 13 for reverse-discrete-cosine-transforming the reverse-quantized count number, received from the reverse quantizing portion 12, in the unit of 8.times.8 blocks; an adding portion 14 for combining an image signal transferred from the IDCT portion 13 and a motion-compensated image signal; a first frame memory 15 of 3 Mb for converting the image signal transferred from the adding portion 14 in the unit of frames; a slice buffer 16 for generating the image signal transferred from the first frame memory 15 in the unit of lines; a second frame memory 17 for converting the image signal transferred from the adding portion 14 in the unit of frames; and a motion compensating portion 18 for motion-compensating the image signal transferred from the second frame memory 17 according to a motion vector from the VLD portion 11, transmitting it to the adding portion 14.
The divided motion vector is transferred into the motion-compensating portion 18, and the quantized value and the count number are fed into the reverse quantizing portion 12.
The reverse quantizing portion 12 reverse-quantizes the count number, received from the VLD portion 11, according to the quantized value. The reverse-quantized count number is restored to the image signal through an IDCT conversion in units of 8.times.8 blocks, and transferred into the adding portion 14.
The adding portion 14 combines the image signal transferred from the IDCT portion 13 and a signal pre-estimated by the second frame memory 17 through a motion compensation to restore the image signal into a complete image, generating it to the first frame memory 15.
The first frame memory 15 converts the image signal transferred from the IDCT portion 13 in the unit of frames and transmits the output to the slice buffer 16, which converts the image signal from the first frame memory 15 in the unit of lines.
The image signal generated by the adding portion 14 is converted by the second frame memory 17 of 6 Mb in the unit of frames. The motion compensating portion 18 compensates the image signal received from the second frame memory 17 according to the motion vector generated from the VLD portion 11, generating it to the adding portion 14.
Since the HDTV video decoder of the prior art decodes many pixels on one screen with an 8.times.8 IDCT, the data to be processed is large in size and requires larger logic circuits and memories.